1. Field of the Invention
The present invention relates to a method for forming stacked films by stacking high permittivity gate dielectrics each having different relative permittivity constants, and for depositing a metal electrode material film on the stacked films, in manufacture of a metal oxide semiconductor field effect transistor (MOSFET). In particular, the present invention relates to a method for causing the Equivalent Oxide Thickness (EOT) of the MOSFET to be equal to or smaller than 1.0 nm.
2. Related Background Art
In manufacture of the MOSFET, today, the MOSFET is manufactured in combination where a silicon dioxide (SiO2) film is used as the gate dielectrics thereof, and polysilicon is used as the gate electrode thereof. In order to improve the performance of an integrated circuit, the design rule thereof has been reduced gradually. Being accompanied with this, thinning of the gate dielectrics is required. However, there is limitation in thinning of the gate dielectrics using the silicon dioxide (SiO2) film. In other words, thinning beyond the limit results in increase of leakage current beyond the tolerance level.
Therefore, today, application of gate dielectrics having a relative permittivity constant larger than that of the silicon dioxide (SiO2) film is considered. The gate dielectrics is referred to as high permittivity gate dielectrics. When the high permittivity gate dielectrics is used as the gate dielectrics, the gate electrode also have to be changed into a metal electrode. It is because of the two reasons described below. A first reason is in that polysilicon does not match with almost all of high permittivity gate dielectrics. A second reason is in that if polysilicon is used, a depletion region is formed in the interface between the polysilicon and the high permittivity gate dielectrics, thereby, the EOT of the MOSFET becomes larger, resulting in reduction of the capacitance thereof.
Here, the Equivalent Oxide thickness (EOT) will be described. The electric film thickness obtained by means of back calculation by assuming the gate dielectrics material is the silicon dioxide (SiO2) film, without depending on the types of the gate dielectrics, is referred to as the EOT (Equivalent Oxide thickness) of the silicon dioxide (SiO2) film. In other words, when the relative permittivity constant of the dielectrics is denoted as ∈h, the relative permittivity constant of the silicon dioxide (SiO2) film is denoted as ∈o, and the thickness of the dielectrics is denoted as dh, the EOT of the silicon dioxide (SiO2) film, de, is represented by the following formula 1.de=dh×(∈o/∈h)  (1)When a material having a relative permittivity constant ∈h being larger than the relative permittivity constant ∈o of the silicon dioxide (SiO2) film is used as the gate dielectrics, the above-mentioned formula 1 indicates that the EOT of the silicon dioxide (SiO2) film becomes equivalent to the thickness of the silicon dioxide (SiO2) film being thinner than the thickness of the gate dielectrics. In addition, the relative permittivity constant ∈o of the silicon dioxide (SiO2) film is an order of 3.9. Therefore, for example, for a film composed of a high permittivity gate dielectrics material having a relative permittivity constant ∈h of 39, even if the physical film thickness of the high permittivity gate dielectrics material is 15 nm, the EOT (electric film thickness) of the silicon dioxide (SiO2) film becomes 1.5 nm, thereby, the tunnel current thereof can be largely reduced, while the capacitance value of the gate dielectrics being caused to be equivalent to that of a silicon dioxide (SiO2) film having a thickness of 1.5 nm.
Today, HfO2, HfSiO or HfSiON has a high degree of expectation as the high permittivity gate dielectrics. Since the relative permittivity constants of them are an order of 10 to 20, being calculated by using the above-mentioned formula 1, the thickness of the dielectrics becomes an order of 6 to 7. However, since in a practical structure a silicon dioxide (SiO2) film having a thickness of an order of 1 nm, is required between the silicon wafer and the high permittivity gate dielectrics, the film thickness of the Hf-based high permittivity gate dielectrics becomes as thin as an order of 1 to 2 nm, it is difficult to reduce the gate leakage current while satisfying the condition: EOT<1 nm.
Therefore, Honda et al. (JJAP Vol. 43 (2004) p. 1571), formed HfO2 film on a Si wafer, stacked SiO2 having a relative permittivity constant being different from that of the HfO2 film, on the HfO2 film, by means of a pulsed laser deposition method, exposed them to atmospheric air, subsequently, formed a metal electrode film, and then evaluated electric properties of the resultant stacked films. As the result, the hysteresis thereof was 50 to 300 mV, and the EOT thereof was greater than 1 nm (H, Watanabe et al., Jpn. J. Appl. Phys. 45 (2006) 2933).
In this manner research of Metal/High-k gate stack has been energetically advanced as the technology of reducing power consumption and improving the performance of the MOSFET. Although it has been reported that a Hf silicate film has excellent properties as a High-k gate dielectrics material, further reduction of the EOT is required. Since Ti-based oxides have a high relative permittivity constant, improving performance of various kinds of High-k film materials by means of adding Ti has been attempted. Moreover, a phenomenon that forming a TiO2 layer by means of a TiN/HfSiON interfacial reaction reduces the leakage current with little increase of the EOT, has been reported (H. Watanabe et al., Jpn. J. Appl. Phys. 45 (2006) 2933).
In the present invention, the object is to provide an optimum structure of a HfTiSiO film for achieving ultra-thin High-k gate dielectrics satisfying the condition: EOT<1 nm. It is a subject to satisfy the conditions: EOT<1.0 nm, low leakage current, and hysteresis<20 mV, by using a stack structure of Hf-based high permittivity gate dielectrics/Ti-based high permittivity gate dielectrics having a relative permittivity constant being different from that of the Hf-based high permittivity gate dielectrics.